This invention relates to the field of solid state electronics and particularly to a process for making heterojunction bipolar transistors (HBTs) on a semiconductor wafer.
HBTs are fabricated on wafers having a layered structure which forms the heterojunction(s) and the p-n junctions of the transistor. This layered structure is produced during growth of the wafer using processes such as molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD).
In order to provide an integrated circuit incorporating the HBTs, it is necessary to isolate the individual HBTs from each other and from other devices on the wafer. In order to provide high fan-out, low power, and high accuracy HBT integrated circuits, it is necessary to use isolation processes which do not greatly reduce the current gain of the transducers. A process which has proven useful to isolate individual circuit elements is the implantation of protons in the material surrounding the circuit element. However, the isolation implant reduces the current gain of the HBT, and there is a continuing need to improve the process and minimize the reduction in current gain caused by the isolation implant.